FPGA Engineer III
Travel Required - Very minimal up to 10% if any required
The FPGA Engineer 3 is responsible for design, implementation, and integration of RTL for LTE and 5GNR radio access points. The FPGA engineer will collaborate with peers across many engineering disciplines on the design of unique programmable logic based wireless solutions. The engineer will participate with hardware, software, and test engineers in bring up, design verification testing (DVT) and end-to-end integration of the final product.
FPGA for high-speed real-time data processing applications
Proficiency with VHDL and scripting languages.
ARM AXI interfaces and DMA
Model based design tools such as DSP Builder and System Generator
Multi-gigabit design (10Gb/s Ethernet, JESD204, 10GBASE-R/KR, or similar)
Clock domain partitioning, timing constraints rules, static timing closure
Hierarchical test bench design
Automated vector stimulus input and output vector pass/fail checking
ChipScope or SignalTap debugger or equivalent methods
Implementation knowledge in the following signal processing areas is highly desirable, Digital NCO, Quadrature Modulator and Demodulator, channel filtering, AGC and PLL and loop filters
LTE or 5GNR Layer 1 radio implementation with end-to-end system integration experience is preferred.
Experience in supporting product development through the entire product lifecycle is highly desirable.
Demonstrated experience developing and integrating designs in a multi-discipline collaborative engineering environment.
Completed bachelors Degree (preferably in EE or Computer Engineering) plus a minimum of 5 years of experience in electronic hardware development or masters degree (preferably in EE or Computer Engineering) plus a minimum of 2 years of experience in electronic hardware development. (Relevant exp would be in FPGA development. Manager wants recent FPGA experience)
4+ years relevant experience in the implementation of high-speed real-time FPGA RTL
How To Apply:
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