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Computer Scientist - ASIC Digital Design
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NPAworldwide Recruitment Network
 
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Job Location: USA-Nationwide, US
JOB DESCRIPTION

Job #: 34668
Title: Computer Scientist - ASIC Digital Design
Job Location: , - United States
Employment Type:
Salary: $125,000.00 - $165,000.00 - US Dollars - Yearly
Other Compensation: Plus 10% 401K and benefits
Employer Will Recruit From: Nationwide
Relocation Paid?: Yes

WHY IS THIS A GREAT OPPORTUNITY?

We are a world leader in the research and development of advanced artificial intelligence, information processing, computing, and communications technologies.

JOB DESCRIPTION

We are a world leader in the research and development of advanced artificial intelligence, information processing, computing, and communications technologies.

*This position is based in Arlington, VA. Remote work options are available *

Our focus is in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools.

As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.

Our staff can be found:

Researching and developing toolsets to map AI algorithms directly to hardware,

Optimizing full scale testing of billion transistor FPGAs to minimal runtime,

Performing experiments on the International Space Station,

Utilizing our MOSIS service to fabricate novel computer architectures.


Our success is based on investing in our staff through a culture centered on:

Learning and idea generation,

Transparent and constructive feedback, and

Continual growth through contributing to, creating, and leading a research agenda.


We are looking for highly talented, motivated researchers to lead research and development in the area of secure hardware.
This position will collaborate with a high caliber team to create the worlds first customized accelerator for native Fully Homomorphic Encryption (FHE).
Utilize custom EDA tools to synthesize, analyze, floorplan, and perform design space exploration of architectures over performance parameters.
Be an active member of fast-paced ASIC Development team supporting the full life cycle from functional architecture definition to physical implementation, verification, and tape-out.
Support efforts analyzing and evaluating the effectiveness of hardware security techniques such as obfuscation, logic locking, or programmability for use in advanced lithography nodes and real-world System on a Chip use cases in terms of quantifiable security, overhead, and useability metrics.
This position will lead research, propose major innovations, collaborate with peers within the group and across the org, publish results in top tier conferences, and contribute to or lead proposals.

JOB QUALIFICATIONS:

PhD or MS and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.

Established publication record in computer architecture, ASIC design, Fully Homomorphic Encryption hardware, or hardware security.

3-5 years of experience in Digital Design targeting 22nm or smaller lithography nodes.

Expert level programming in Synthesizable C, VHDL, or Verilog.

Experience interfacing and floor planning with bus (PCIe gen 4/5) memory (DDR3/4), and Single/Differential-ended I/Os in System on Chip designs.

Expert level user of standard digital design tools such as Cadence Stratus, Genus, and Innovus or Synopsys Synphony, Design Compiler, and IC compiler.


Preferred Job Qualifications:

Experience targeting 12nm or smaller fabrication nodes a significant plus.

Experience with clock tree insertion, scan-chain insertion, and back end layout a plus.

Experience with Cadence JasperGold or Synopsys Formality a plus.

QUALIFICATIONS

JOB QUALIFICATIONS:

PhD or MS and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.

Established publication record in computer architecture, ASIC design, Fully Homomorphic Encryption hardware, or hardware security.

3-5 years of experience in Digital Design targeting 22nm or smaller lithography nodes.

Expert level programming in Synthesizable C, VHDL, or Verilog.

Experience interfacing and floor planning with bus (PCIe gen 4/5) memory (DDR3/4), and Single/Differential-ended I/Os in System on Chip designs.

Expert level user of standard digital design tools such as Cadence Stratus, Genus, and Innovus or Synopsys Synphony, Design Compiler, and IC compiler.


Preferred Job Qualifications:

Experience targeting 12nm or smaller fabrication nodes a significant plus.

Experience with clock tree insertion, scan-chain insertion, and back end layout a plus.

Experience with Cadence JasperGold or Synopsys Formality a plus.

Education:
University - PhD




How to Apply:


 
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